EECS 478: Logic Circuit Synthesis and Optimization

This page is a placeholder. The full syllabus, schedule, and project materials will be posted before the term begins. Details below may change.

About the course

How a description of hardware becomes an optimized circuit. The course covers representations of Boolean functions (BDDs, CNF, and-inverter graphs) and the engines that reason about them, especially SAT solvers; two-level and multi-level logic minimization, don't cares, technology mapping, sequential synthesis and verification, and high-level synthesis. The algorithms are studied alongside the open-source tools that implement them, such as ABC and Yosys.

Coursework includes three C++ programming projects (a BDD package, a SAT solver, and an AIG optimizer), homework, an in-class midterm, and a cumulative final exam. Students should be comfortable writing C++ at the level of EECS 281.

Logistics

Key dates